While solder bumps are increasingly becoming a common means of electrically connecting a semiconductor die to its next level substrate in a flip-chip configuration, wire bonded semiconductor devices remain the most common form of products sold in the semiconductor industry. For purposes of lowering costs, it would be advantageous if a semiconductor manufacturer could use as many common manufacturing operations for the two types of devices as possible.
One area of manufacturing where the process flow of the two types of devices tends to diverge is testing. Wire-bonded devices are usually tested much differently than their flip-chip counterparts. Wire bonded devices are typically burned-in and functionally tested after the die has been fully packaged (e.g. after the die has been wire bonded to leads of a lead frame and encapsulated in a plastic or ceramic package body). The external package leads are used to make the necessary electrical connections for testing. With bumped die to be flip-chip mounted directly onto the board, an external package is not used. For example, a bumped die may be sold directly to a customer for direct chip attach (DCA) to the customer's printed circuit board. In this situation, the semiconductor manufacturer must test the die without the luxury of having a leaded package.
One method of testing at the die level is to use probe needles or pins which make physical and electrical contact with input/output (I/O) and power pads of the device, usually while the die are still in wafer form. However, probing is difficult once the device has been bumped. Not only is contact between the bumps and needles difficult to make, but damage to the bumps is possible. Probe needles cannot practically be used during high-temperature testing (e.g. at burn-in) because the needles tend to move too much, losing electrical connection to the bumps or pads during the test. Furthermore, burn-in requires long test time where utilizing expensive testers is not practical.
Another wafer-level testing method is to form a sacrificial conductive layer, such as copper, over the device and to use this conductive layer to test the device, for example as described in U.S. Pat. No. 5,399,505 by Dasse et al. A disadvantage of this technique is that as the wafer becomes larger and as device geometry pitches become smaller, it is difficult to establish routing connections to those die near the center of the wafer. One method of guaranteeing access to the center of the wafer is to employ multiple sacrificial conductive layers to route signals, but this significantly adds to the manufacturing cost of the wafer.
Another approach for testing unpackaged die is the use of test sockets which are specially designed for use with bare die. The primary disadvantages of this method are the high cost of each socket, and thus the test board cost, handling of bare die, and the complications associated with loading and unloading each socket on the board. Furthermore, such test sockets cannot be used to test devices at the wafer level thereby eliminating the ability to supply product in wafer form.
U.S. Pat. No. 5,447,264 by Koopman et al. discloses a method for testing bare die which uses a temporary testing substrate that also serves to transfer solder bumps to the device tested. Solder is electroplated through a via opening in a passivation layer of the temporary substrate, and into an etched trench underlying the via. The solder also extends onto the passivation layer adjacent to the via. The plated solder "islands" are then aligned to, and brought into physical contact with, the I/O pads of a semiconductor die. The composite structure is then heated and cooled to form a solid phase mechanical and electrical connection between the semiconductor device and the temporary substrate. Testing is performed, then a shearing or pulling force is applied between the device and the temporary substrate to cause the solder bump to fracture at the temporary substrate, leaving the solder on the I/O pads of the device. While the method disclosed in U.S. Pat. No. 5,447,264 has several advantages over the other mentioned prior art techniques for testing at the die or wafer level, the method is limited to use die which are to be bumped (i.e. flip-chip die).
Accordingly, a need exists for a method for testing semiconductor devices which is conducive to use with both flip-chip die or wire-bonded die designs so that manufacturing flows of the two devices can be kept as common as possible. Ideally, such a method would be performed at the die or wafer level to prevent unnecessarily packaging non-functional or weak devices and would impose minimal cost to the manufacturing operation. It is also desirable for such a method to enable a common die design for the two different device types.